Concept

Physical design (electronics)

Related publications (29)

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

Mirjana Stojilovic

Side-channel CPU disassembly is a side-channel attack that allows an adversary to recover instructions executed by a processor. Not only does such an attack compromise code confidentiality, it can also reveal critical information on the system’s internals. ...

IEEE2022

Design and management of three-dimensional multi-processor systems-on-chip with integrated flow cell arrays

Halima Najibi

Three-Dimensional Multi-Processor Systems-on-Chip (3D MPSoCs) are promising solutions for highly intensive Artificial Intelligence (AI) and Big Data applications. They combine remarkably dense computation capabilities and massive communication bandwidths. ...

EPFL2022

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Paolo Ienne, Grace Zgheib, Stefan Nikolic

In this work, we develop timing-driven CAD support for FPGA architectures with direct connections between LUTs. We do so by proposing an efficient ILP-based detailed placer, which moves a carefully selected subset of LUTs from their original positions, so ...

ASSOC COMPUTING MACHINERY2022

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Arin Can Ülkü, Andrei Ardelean, Paul Mos, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Challenges and Opportunities of Edge AI for Next-Generation Implantable BMIs

Mahsa Shoaran, Mohammad Ali Shaeri, Arshia Afzal

Neuroscience and neurotechnology are currently being revolutionized by artificial intelligence (AI) and machine learning. AI is widely used to study and interpret neural signals (analytical applications), assist people with disabilities (prosthetic applica ...

IEEE2022

Geometrical Treatise on the Modelling of 3D Particulate Inclusion-Matrix Microstructures with an Application to Historical Stone Masonry Walls

Mahmoud S. M. Shaqfa

As historical stone masonry structures are vulnerable and prone to damage in earthquakes, investigating their structural integrity is important to reduce injuries and casualties while preserving their historical value. Stone masonry is a composite material ...

EPFL2022

LUT-Based Optimization For ASIC Design Flow

Giovanni De Micheli, Eleonora Testa, Luca Gaetano Amarù

In this paper, we develop a new LUT-based optimization flow tailored for the synthesis of ASICs rather than FPGAs. We enhance LUT-mapping to consider the literal/AIG cost of LUT-nodes. We extend traditional Boolean methods to simplify and re-shape LUT-netw ...

2021

Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction

Christian Enz, Minhao Yang

Ultralow-power sensing with inference functionality embedded in sensor nodes is essential for enabling the emerging pervasive intelligence. For acoustic inference sensing, the feature extraction can take advantage of power-efficient analog circuits. Howeve ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Design-to-Fabrication Workflow for Raw-Sawn-Timber using Joinery Solver

Petras Vestartas

Currently, the Swiss timber industry in mountain areas largely exports unprocessed lumber and imports finished timber products due to the lack of digital tools. By using new digital design-to-production workflows, it is possible to investigate new building ...

EPFL2021

Data Structures and Algorithms for Logic Synthesis in Advanced Technologies

Eleonora Testa

Logic synthesis is a key component of digital design and modern EDA tools; it is thus an essential instrument for the design of leading-edge chips and to push the limits of their performance. In the last decades, the electronic circuits community has evolv ...

EPFL2020

Extending Boolean Methods for Scalable Logic Synthesis

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon, Eleonora Testa, Luca Gaetano Amarù

In recent years, Boolean methods in logic synthesis have been drawing the attention of EDA researchers due to the continuous push to advance quality of results. Boolean methods require high computational cost, as they rely on complete functional properties ...

2020

High fill-factor miniaturized SPAD arrays with a guard-ring-sharing technique

Edoardo Charbon, Kazuhiro Morimoto

We present a novel guard-ring-sharing technique to push the limit of SPAD pixel miniaturization, and to demonstrate the operation of SPAD arrays with a 2.2 mu m-pitch, the smallest ever reported. Device simulation and preliminary tests suggest that the opt ...

2020

High-Performance III-V MOSFETs and Tunnel-FETs Integrated on Silicon

Clarissa Convertino

Silicon transistor scaling is approaching its end and a transition to novel materials and device concepts is more than ever essential. High-mobility compound semiconductors are considered promising candidates to replace silicon, targeting low-power logic a ...

EPFL2020

Optical-stack optimization for improved SPAD photon detection efficiency

Edoardo Charbon, Claudio Bruschini, Rolando Ferrini, Arin Can Ülkü, Ivan Michel Antolovic, Scott Anthony Lindner, Ekin Kizilkan, Frédéric Zanella

Single-photon avalanche diodes (SPADs) are direct photon-to-digital detectors that enable scalable arrays with Poisson-limited signal-to-noise ratio and picosecond timing resolution. However, SPAD detectors require a guard-ring structure to prevent lateral ...

2019

SPADE: Tuning scale-out OLTP on modern RDMA clusters

Rachid Guerraoui, Aleksandar Dragojevic, Georgios Chatzopoulos

Distributed transactions on modern RDMA clusters promise high throughput and low latency for scale-out workloads. As such, they can be particularly beneficial to large OLTP workloads, which require both. However, achieving good performance requires tuning ...

Association for Computing Machinery2018

Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow

Edoardo Charbon, Francesco Regazzoni

This work proposes the first fine-grained configurable cell array specifically tailored for the implementation of cryptographic algorithms that can be configured using widely adopted hardware description languages. Our solution can be added as a small, cry ...

IEEE2018

End-to-End Industrial Study of Retiming

Giovanni De Micheli, Cunxi Yu

Sequential circuits are combinational circuits that are separated by registers. Retiming is considered as the most promising technique for optimizing sequential circuits, that involves moving the edge-triggered registers across the combinational logic with ...

IEEE2018

Ordering Events Based on Intentionality in Cyber-Physical Systems

Jean-Yves Le Boudec, Simon Bliudze, Wajeb Saab, Maaz Mashood Mohiuddin

We consider cyber-physical systems (CPSs) comprising a central controller that might be replicated for high-reliability, and one or more process agents. The controller receives measurements from process agents, causing it to compute and issue setpoints tha ...

2018

Ordering Events Based on Intentionality in Cyber-Physical Systems

Jean-Yves Le Boudec, Simon Bliudze, Wajeb Saab, Maaz Mashood Mohiuddin

2017