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Concept

Loop unrolling

Related publications (7)

An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs

David Atienza Alonso, Giovanni Ansaloni, Miguel Peon Quiros, Flavio Ponzina

Codebook-based optimizations are a class of algorithmic-level transformations able to effectively reduce the computing and memory requirements of Convolutional Neural Networks (CNNs). This approach tightly limits the number of unique weights in each layer, ...

2022

Gradient-Based Learning of Discrete Structured Measurement Operators for Signal Recovery

Jonathan Paul Sauder

Countless signal processing applications include the reconstruction of signals from few indirect linear measurements. The design of effective measurement operators is typically constrained by the underlying hardware and physics, posing a challenging and of ...

2022

Uncooperative Rendezvous in Space: Design of an Electronic Architecture for High Performance Avionic with Multi Sensor Input and Intensive Data Rate

Michaël Yannick Juillard

Active Debris Removal missions consist of sending a satellite in space and removing one or more debris from their current orbit. A key challenge is to obtain information about the uncooperative target. By gathering the velocity, position, and rotation of t ...

EPFL2022

Noninvasive Cardiac Output and Central Systolic Pressure From Cuff-Pressure and Pulse Wave Velocity

Nikolaos Stergiopoulos, Vasiliki Bikia, Bram Trachet, Stamatia Zoi Pagoulatou

Goal: We introduce a novel approach to estimate cardiac output (CO) and central systolic blood pressure (cSBP) from noninvasive measurements of peripheral cuff-pressure and carotid-to-femoral pulse wave velocity (cf-PWV). Methods: The adjustment of a previ ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Hardware-in-the-Loop Validation of an FPGA-Based Real-Time Simulator for Power Electronics Applications

Farhad Rachidi-Haeri, Mario Paolone, Reza Razzaghi

This paper presents the hardware-in-the-loop (HIL) validation of a proposed FPGA-based real-time simulator for power electronics applications. The proposed FPGA-based real-time simulation platform integrates the Modified Nodal Analysis (MNA) method, Fixed ...

ipst.org2015

A parametric AC loss model of the ITER coils for control optimization

A recent study on AC loss calculation in different operating regimes of relevance for ITER plasma control has shown that AC loss calculations can be performed on a model with a level of complexity and completeness not achieved so far [L. Bottura, P Bruzzon ...

Elsevier2010

Temporal instruction fetch streaming

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman

L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough to capture the application, library, and OS instruction working sets of these wo ...

2008